And ARM (or even x86) MCU/CPU with von Neumann structure, its address space is unified and continuous, code memory/RAM/CPU registers, and even PC video memory are all addressed uniformly. It's just that memory with different functions occupies different address blocks, and they do their own things.
Okay, let's go back to MCS-51.
For program memory, there are two parts: on-chip and off-chip. And regardless of the on-chip program memory or the off-chip program memory, their addresses are shared. If there is 4k ROM on-chip, the address is 0x0000-0x0FFF, and 0x1000-0xFFFF is the address space of the external ROM. Whether the 0x0000-0x0FFF part of the external ROM is used, it depends on the level value of the EA pin of the microcontroller. When EA=1, this part of the internal ROM is used, and this part of the external ROM is wasted and not used; when EA=0, this part of the external ROM is used, and the internal ROM is wasted and not used. To read data from the CODE segment, use the assembled MOVC instruction. The single-chip microcomputer will automatically determine which memory to fetch data from according to the MOVC instruction, EA status, and the address value to be read
For data memory, it is divided into two parts: internal data memory (IDATA/RAM) and external data memory (XDATA), but these two memories do not share the address space like code memory. The general 8051 chip, the internal RAM is only 128B, from 0x00-0x7F, and from 0x80-0xFF is the area of SFR (CPU working registers and various peripheral registers are here). For the 8052, the internal RAM has 256B, so 0x80-0xFF is the high 128B RAM in use. But isn't this part dedicated to SFR? It's dedicated to SFR, but note that SFR access can only use "direct addressing" (implemented using specific assembly instructions), the difference is here. Only the address accessed by direct addressing is SFR, otherwise it is ordinary RAM. As for the extended RAM (XDATA), the address is also from 0x0000-0xFFFF, and the 0x0000 here is different from the 0x00 of the internal RAM, and they are completely independent of two spaces. Their access methods are also different. MCS-51 uses MOVX instruction to read and write XDATA area. Moreover, access to the XDATA area requires the assistance of the DPTR register. Because only DPTR can hold the next 16-bit XDATA address.
So, MCS-51 has the fastest reading and writing speed of IDATA area and the most access methods. The speed of accessing the XDATA area is relatively slow. The stack of MCS-51 should be developed in the IDATA area first, and the stack opened in the IDATA area can be controlled by the stack pointer register SP. If the stack is really too big and can only be opened in the XDATA area, then the SP register of the CPU will be difficult to borrow, and we can only construct the stack structure and stack pointer by ourselves. Since the external program space and data space are both 0-64K (0x0000-0xFFFF), then I can actually save trouble/convenient rewrite programs and other reasons, the external CODE and DATA can share a rewritable memory (such as various What RAM can be erased and writable). For example, the system has a 64K external MEMORY. The lower 32K is used to save the CODE, and the microcontroller can read and run the program in this 32K, and the higher 32K is used as the storage place for user data. But at this time, the originally completely independent CODE and DATA space, because a MEMORY is shared on the hardware chip, they may affect each other, and the program can rewrite the program by itself. For example, 0x0020 is an instruction, and I rewrite 0x0020 through MOVX, then use MOVC to read out 0x0020, and the data is different from the original.
The crux of confusion is that the storage space of the single-chip microcomputer is a logical concept, which is two separate spaces that are artificially divided. The MEMORY chip on the hardware circuit is a concept in reality. The storage space of the single-chip microcomputer will eventually be implemented on the chip at the circuit level, so the logical storage space will overlap due to the physical circuit connection. But at the logical level, these two spaces are still completely independent.
Attachment: Definition of various storage space names:
Data: fixedly refer to the 128 RAMs of 0x00-0x7f in the front, which can be directly read and written by a register, the fastest and the smallest generated code.
Idata: fixedly refers to the 256 RAMs of 0x00-0xff in the front, of which the first 128 is exactly the same as the 128 of data, just because of the different access methods. idata is accessed using a pointer similar to C. The statement in the assembly is: mov ACC,@Rx. (not important supplement: idata in c has a good pointer access effect) xdata: external extended RAM, generally refers to the external 0x0000-0xffff space, which is accessed by DPTR. pdata: the lower 256 bytes of the external extended RAM, read and write when the address appears on A0-A7, use movx ACC, @Rx to read and write. This is quite special, and C51 seems to have this bug, it is recommended to use less. But there are also his advantages. The specific usage is an intermediate problem, I don't know how to use it, so I won't mention it here.